1. Field of the Invention
This invention relates to a semiconductor memory device, especially to an electrically rewritable and non-volatile memory (EEPROM).
2. Description of Related Art
As one of EEPROMs, a NAND-type flash memory is known. In the NAND-type flash memory, data write and read are performed page by page. Data write is performed with a write voltage application and a write-verify repeated. To judge internally whether the entire bits in a page have been written or not, there is usually prepared a batch verify circuit (for example, refer to Unexamined Japanese Patent Application Publication No. 2001-250395).
In case the flash memory system has an ECC function inside or outside of the chip, it will be permitted in relation to the ECC function that there are certain fails (i.e., bit fail number or column fail number). Therefore, it is desired in case data write ends in “Fail” that the fail number being detected and judged under a “permissible fail number”, it is dealt with “Pseudo-Pass”. Considering this point, there has already been provided such a flash memory that Pass/Fail detection is made possible in relation to the permissible fail number (for example, refer to Unexamined Japanese Patent Application Publication No. 2002-140899).
Usually, in a flash memory with a large capacitance, a redundancy system is used for defect-relieving. For this purpose, there is prepared a redundant cell array for replacing a defect (for example, defect column) detected in a test before shipment with a redundant column therein. Further in the memory chip, there are prepared a defect address storage circuit and an address match detecting circuit for detecting address matching between an externally supplied address and a defect address stored in the defect address storage circuit. With these circuits, defective address replacing control may be performed.